FIG. 1 illustrates a block diagram of a prior art bus mechanism to establish a connection path between initiator network resources to target network resources across a bus. The network may consist of various network resources that may initiate requests such as initiating network resources 1 through N, where N indicates any number. The network may also contain target network resources, which will service the requests of the initiating network resources. The target network resource may contain target network resources such as target network resources 1 through N. The system may contain a bus controller for controlling the transactions between the initiator network resource and the target network resource. FIG. 1 illustrates with dotted lines, a connection path from the first initiator network resource across the common data bus to the second target network resource.
Digital signals from the initiating network resource to the target network resource vary the voltage level on the conductive pathways to transition the voltage level from a low voltage to a high voltage and vice versa to communicate the data in the digital signal. Transitioning a set of conductors causes two things to occur when those conductive pathways transition. First, the conductive pathways must consume power to charge up from a low voltage state to a high voltage state. Next, the conductive pathways adjacent to the conductive pathways transitioning from a high voltage state to a low voltage state may incur current leakage flow through the capacitance between the neighboring lines. A small amount of leakage current flows out from the adjacent lines causing those lines to have to be recharged more often to replace the leaked charge. The more often those conductive pathways have to be recharged, the more power is consumed, and that means a lower battery life for hand held devices.
In some previous common bus techniques, when the first initiator network resource communicates a data payload across the common data bus to the second target network resource, not only will the direct pathway between the initiator and target have a voltage transition but most of the lines and pathways associated with that data bus may also transition their voltage levels at the same time. In this prior approach used by shared interconnects and buses, generally there has been little effort made to reduce voltage transitions on conductive pathways not directly involved in the transaction transfer between the initiator network resource and the target network resource.
Also, two generic types of arbitration controllers typically exist. The first type of bus controller locks the bus until a target network resource is ready to accept a transition if an initiator wins the arbitration process. With this type of arbitration controller, the overall system performance typically is reduced because all of the other network resources must wait on the target resource to be ready to service the initiator who won the arbitration process prior to getting another transaction processed across that shared interconnect. The second type of bus controller transmits the payload of information to the target network resources when an initiator network resource wins the arbitration process. If the target network resource is not ready to service the information sent across from the initiator, then the target network resource sends a retry response to the initiator. This type of bus control mechanism wastes power. The initiating network resource on every cycle may send information across the shared link. However, the transmitted information may need to be retransmitted several times before that information is actually serviced by the target network resource.
Also, in some dedicated interconnects that couple to a single initiator and a single target a form of transition filtering has been applied to the set of wires for the dedicated communication between a single initiator and a single target. However, typically these dedicated interconnects have no need for an arbitration mechanism to share the dedicated wires.
Further, some system on chip designs are beginning to suffer potential performance problems because of the physical distance traveled on the chip for a fully combinational initiation of a request and payload transmission occurring in the same cycle. For a single cycle arbitration and payload transfer, the initiator sends a request from its location on the chip to the arbitration controller. The arbitration controller conducts an arbitration of all of the requests being presented to select a winning request. The arbitration controller, from its location on the chip, sends back the response granting the request to the initiator. The initiator sends the payload of information from its location on the chip across the interconnect to the target network resource at its location on the chip. All of these steps occur in the same cycle. The signals travel a physical distance multiple times to and from the arbitration controller and once from the initiating network resource across the interconnect to a target network resource. A measurable amount of time takes place for the electrons to travel that distance. Thus, the speed of the clock clocking that particular circuit may be capped to a maximum amount so that a worst case physical distance needed to travel by the electrons across the chip can occur within a single cycle. The worst case physical distance needed to travel by the electrons across the chip can limit how fast the clock speed a particular chip may operate at.